1. Technical Field
The present invention relates generally to semiconductor chip packaging. More particularly, the present invention relates to a non-planar semiconductor chip, and a method of forming the non-planar semiconductor chip.
2. Related Art
In the manufacture of semiconductor chip packages, such as laminate chip carriers, differences in the coefficients of thermal expansion, in combination with thermal cycling, tend to produce high stresses in locations of abrupt geometric change within the chip. During thermal cycling the chip may bend creating a stress concentration between the outer edges of the chip and the package cover plate, heat sink, or other device mounted thereon, as well as the adhesive materials therebetween. In addition, high localized stresses tend to occur at the edges of organic chip carrier packages, having heat spreaders or coupled caps, due to the differences in curvature of the various layers. Further, flaws, such as voids, cracks, etc., within the edges or corners of the chip may lead to crack propagation, particularly in locations of abrupt geometric change. As a result, chips may become cracked and/or delamination may occur between the chip, cover plate, and the adhesive material therebetween.
Attempts have been made in the industry to minimize the amount of stress concentrations within the chip packages. For instance, the thickness of the chip has been reduced in an attempt to make the chip more flexible, thereby minimizing the stress concentrations. The thickness of the cover plate or heat sink has been reduced near the edges of the cover plate or heat sink in an attempt to increase flexibility as well. Additionally, attempts have been made to minimize the amount of thermal mismatch between the chip, cover plate or heat sink and the adhesives in contact with the chip.
Accordingly, there currently exists a need in the industry for a semiconductor chip package having reduced stress concentrations therein.